The present invention relates to a microprocessor having bus cycle control means.
In a processor system comprising a microprocessor and plural memories, when the system configuration is of large scale, an asynchronous bus control system is used because it is necessary to connect with external devices, such as memories having different access times, through a bus.
FIG. 5 shows a configuration of a processor system of an asynchronous bus control type which was proposed by some of the inventors of the present invention and others, but was not known prior to the priority date of the present invention. A microprocessor 500 and external devices 150 and 151 are connected through an asynchronous transmission bus 130.
In this system, a bus cycle starts when a control unit 101 in the microprocessor 500 produces an address signal on line 132. When the address signal on line 132 is established, an asynchronous bus control circuit 103 asserts an address valid signal A.V. on line 134 at the timing of the address signal on line 132. Accessing of the external devices 150 and 151 is started after the assertion of the address valid signal on line 134 has been confirmed. An access end detector 140 arranged externally of the microprocessor 500 monitors the address signal on line 132 and address valid signal 134, and provides a data complete signal D.C. on line 141 after a bus cycle time required for the external device being accessed. The microprocessor 500 reads in the data complete signal D.C. from line 141 and produces at least one of a wait release signal WAIT on line 104 and bus cycle end signal END on line 105 to the asynchronous bus control circuit 103 through a synchronizing circuit 102 which synchronizes the timing to an internal clock. Thus, the control unit 101 detects the end of one bus cycle and starts the next bus cycle if required. FIG. 6 shows a timing chart of such asynchronous bus control.
In the asynchronous bus control system, it is necessary to provide the access end detector 140 externally of the microprocessor to generate the data complete signal to terminate the bus cycle. When such an access end detector is arranged externally of the microprocessor, not only the hardware increases, but also the generation of the data complete signal is delayed because the generation logic therefor is complex, and the bus cycle is extended.